Verilog Interview Questions to Prepare in 2021

Verilog Interview Questions

Verilog is a Hardware Description Language(HDL). We will discuss Verilog Interview Questions here. Language is used to explain a digital system like a network switch, microprocessors, memory, or flip-flop. To simplify the work of people in designing the integrated circuits, drawing transistors and connections, VHDL came into use. Verilog only asks the user to input the ideation, and the automatic tools convert it into actual hardware using logic gates and sequential gates.

Verilog Interview Questions

  • Give yourself a rating on this software.

This question is to test your confidence and how much you know about the subject in your opinion. This can also be a testing factor for them, so answer it honestly. Do not give yourself extra credits or fewer credits. If you take extra credits, they might judge you on your skills afterward, and giving yourself fewer credits may give them the impression that you are not good in the software and may even half-mindedly move further. So be sure to give accurate points to yourself.

  • What is a hardware schematic?

It is a pictorial representation of the use of gates to achieve a particular hardware functionality. We can encapsulate the internal details in a black box if we know the combination to attain the result. The block gives us a result similar to a hardware diagram which is made using combinational gates.

  • Tell us about some Verilog-supported designs.

Verilog supports many designs at many levels. Some of them are categorized as important like the follows:

  1. Behavioral Level: It is sequential, which means the set of commands is executed one by one. The main elements are blocks, functions, etc.

  2. Register-Transfer Level: It specifies the characteristics of a circuit by the transfer of data and operations between the registers. Any synthesizable code is called an RTL code.

  3. Gate Level: The features of a system are defined by logical links and their timing properties within a logical level. They can only have definite logical values. For logical designing, it may not come as the best option. GSynthesis tools make gate-level code. For the simulation and back end, his netlist is used.

  4. Others:
    • Lexical Tokens: One or more characters comprise a token. Each character is in a token. The basic tokens are the same as the C programming language like keywords, identifiers, variables, etc. The language is case-sensitive, and all keywords are in small cases.
    • White Spaces: They can contain characters for spaces, tabs, newlines, etc. If they are not treated as another token, they are mostly ignored. In most languages, white spaces include blank spaces, tabs, etc.
    • Comments: They are extra lines used to explain codes that are not included in the run of the code. There are two ways:- Single line using // and double line using /* and ending with */.
    • Numbers: We can give all types of numbers like binary,octal and hexadecimal. Syntax:- <size> <radix> <value>
    • Identifiers: It is used to define the name of variables, functions, objects, etc.
    • Operators: To operate variables and set up a relation. Eg :- >,+,= etc.
    • Keywords: They are predefined words by the coder of language to make language easy and uniform.
  • Explain For loop with an example.

The keyword for the loop is for. The loop mainly consists of three parts that are as follows:

  • Initialization: The loop is given an initial value of signals.
  • Evaluation: The next part is to check whether the condition provided is true and could be executed.
  • Step-value: The change in the initial value for the next iteration.

All three parts of the loop are given initially, unlike the while loop, which is more generally used when the loop has to be iterated as long as the condition is true. The for loop has a start and end defined by change or step value.

For eg:

always@(d or e) begin

For (j=0; j<20; j=i+1) begin

       d<=d+1; //executes the loop for 20 times



  • Give us the name of data types available in Verilog.

Data types are the elements that define how data will act in a program. There are many types of data types supported by Verilog. Some of them are as follows:

  • Wires
  • Registers
  • Input, Output, Inout
  • Integers 
  • Operators
  • Operands
  • Tell us something about operators along with their types.

Operators are basic elements that help us to perform basic to high-level programming such as logic.

  • Arithmetic Operators: They are mostly used for basic or complicated math problems of addition, subtraction, multiplication, division, etc.
    • h=b+d
    • i=d-v
  • Relational Operators: They revert the result as a single bit, either 0 or 1, by comparing two operands. Some of the operators used along with their work are as follows:
    • <= less than or equal
    • == equal to
    • != not equal to 
    • < less than
    • >greater than
    • >= greater than or equal to

  • Bitwise Operators: They make the comparison of every bit. Some of the examples, along with their tasks, are as follows:
    • Bitwise AND &
    • Bitwise OR |
    • Bitwise XOR ^
    • Bitwise XNOR ~^ or ^~

  • Logical Operators: They mostly give single-bit results and also work on single operands. They can work with expressions, variables, etc. For working with expressions they are mostly used in conditional commands. Some of them, along with their symbols, are as follows:
    • Logical Not!
    • Logical And &&
    • Logical OR ||

  • Reduction Operators: They operate on an operand vector of all bits giving the result a single value. They are mostly said as the unary form of Bitwise operators. Some of them are stated as follows:
    • Reduction NOR ~|
    • Reduction NAND ~&
    • Reduction XOR ^
    • Reduction XNOR ~^

  • Shift Operators: The first operand is shifted by the number of bits by the second one in syntax. If no value is provided, then it is automatically fed as zero. Some of them are:
    • << shift left 
    • >> shift right

  • Replication Operator: It prints many copies of an item. The operator used is {n(item)} replicated n folds

  • Conditional Operator: It helps in running a set of commands based on whether the condition is true or false.
    • Syntax: Condition? The result if the condition is true – The result if the condition is false
  • Define Gate Level Modelling.

There are in-built libraries that are rarely used for drawing but used in real-world applications.

There are two major properties:

  1. Drive Strength: The intensity of the output depends on the type of connection between. If the connection is direct, it is maximum, whereas it keeps on decreasing in conducting transistor and pull-up/downs resistor, respectively. It is mostly not mentioned, but defaults are strong1 and strong0.

  2. Delays: If the delay is absent, then there are no propagation delays between the gates. But if it is mentioned, then the first one is a rise, and another one is a fall. In the case of only one mention then both rise and fall are equal.
  • Give some examples of Gate primitives.

Gate uses keywords like and, or, XOR, etc. for one output when input is N integers


  • Reg t0, t1, t2, it3;
  • Not B1(o0, t0);
  • Xor B2(o1, t1, t2, t3);
  • And B3(o2, t2, t3, t0);
  • Define Transmission Primitive gates.

This includes both buffers and inverters. They have several outputs for one input. Example:- Not, buf, bufifo, etc.

  • Reg t0,t1;
  • Not B1(o0,t0);
  • Buf B2(o0,t0);
  • What is the difference between while and for loop?

The while loop tests the condition after a loop is completed, whereas for loop doesn’t start without checking the condition. Mostly the while loop is used if we want to run for a given condition.

  • Tell some ways to define modules.

Modules are blocks of sentences that perform a specified task. There are mainly two ways to declare a module:

  1. Module Declaration: The lines specify the name and port list, and the next few lines define the input/ output width. The default width and port are 1 bit and wire, respectively. Example: module sub_add(add, in1, in2, out);

  2. Continuous Assignment: For assigning a value to a wire, it is used. This is mostly done by explicit assign statements and is consciously changed with every simulation.


  • Assign t=a|b
  • Assign h=c & d
  1. Module Instantiations: Instantiations are done inside other modules for every bit except for the top-level module. They are templates for real objects.
  • Tell us the name of the operands.

Some of the examples are as follows:

  • Literals: They are operands that have a constant value. The two used ones are:
    • String: They are dimensional arrays enclosed in double quotes.
    • Numeric: A number in the octal, hexadecimal, and binary.


  • n- number of bits
  • F- possible formats
  • o- octal
  • d- decimal
  • h- hexadecimal
  • Bit- Selection and Part- Selection: They select one or more bits from different vectors like wire, reg, etc., using []. They are used in the same way as the main data objectives.


  • b=t[7] & s[7]
  • e=h[7:4] + g[3:0]
  • Function Calls: It is used to call a function in an expression regardless of assigning them to a variable. The user must keep the bit of the return value in mind while using it.

Syntax: Function chk_yz;

  • Define wires.

Wires are used for the connection of gates and modules. Its value can only be read and can not store value. The wire is driven by continuous assignment or by connection to an output gate.

Some specific types of wire:

  • Wand (wired and)
  • Wor (wired or)
  • Tri (three-state)


  • Wor[msb:lsb] variable list
  • Wand [msb:lsb] variable list
  • What are arrays?

A scalar or vector variable or net declared is known as an array. After the identifier name, we specify the number of dimensions that can be many, and this type of array is called a multidimensional array. The particular element of an array can be accessed by using an index, and arrays support all types of data types in Verilog.






  • Since we are talking about arrays, please also define memories.

Data and information in digital circuits are stored in digital storage elements known as memories. The best example of memories is RAM and ROM. The use of one-dimensional arrays can do the meddling in storage elements.

Verilog can be a great language to use to make complicated circuits and save time. It is one of the devices that can be used due to its many features and easy-to-use elements. This may take time to learn, but the world is growing faster, and it may help you be a bit ahead of society.

Also read Verilog for Loop – Syntax, and Examples

Verilog Interview Questions to Prepare in 2021

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