Hardware and software both in some ways or other rule the entire system of work. Be it medical, finance, designing, or programming field almost every profession embeds more than one hardware in their professional use. Designing these can be a tricky business, but what makes it more efficient for designers to visualize these networks – Its Verilog. The topic is Array in Verilog.
Be it visualizing a design with the help of a simulator or understanding the timing constraints everything can be effectively carried out using this platform. To leverage the performance of the simulator the language also has different data types like arrays that help in easy visualization of the problem and help in the effective grouping of data according to the system demands. It also allows for easy manipulation of data. Verilog has built-in array types like nets, regs, and other types.
Let us understand all about Verilog arrays in the further section.
What is Verilog?
Verilog is a Hardware Descriptive Language. It is used by programmers to visualize several products that are embedded in machines, these include a switch, microprocessors, flip flops, registers, memory and so much more. It helps to make the working and any HDL robust and flexible. It helps engineers to visualize hardware and study its functionality by experimenting with combinational logic and sequential logic designs.
The simulator designed for the working of Verilog helps in the abstraction of details implemented in the technology and provides us with ways in which we can effectively understand the process of system design. Apart from design the platform also helps us in understanding different system requirements like Power dissipation, timing, and the ability to drive nets and other flops.
What are arrays?
Before getting started with Verilog arrays, let us first understand how simple Arrays function. Understanding the array functions will help you understand the specific roles of arrays in Verilog and help you implement them effectively in Hardware design.
Arrays in simple words can be defined as a queue that helps the system to collect and store data of similar data types. Arrays are usually defined to store data that are placed in the contiguous memory locations and allow for easy manipulation of data. The data stored in the array can be accessed directly through indexing, that is by using the index values assigned to the array.
Arrays prove very useful in applications wherein you require to store a lot of data. It helps in reducing the memory space of the program by avoiding the redundant use of variables, which are practically impossible to memorize for large data.
Now, that you have a basic idea about arrays let us dive into Verilog Arrays.
What are Verilog Arrays?
Verilog arrays work similarly to traditional arrays. They are typically implemented in a program to group elements into a dimension and manipulate the data easily and effectively. Though the function performed by the Verilog arrays are similar, a slight difference occurs in its declaration. In Verilog arrays, users are restricted to use built-in types like nets, regs, and other variable types.
All the arrays that are defined in the system are declared using a maximum and minimum index value that is enclosed in square brackets. There are significantly two ways to write the index,
- Least to most significant index
Array_name [least_significant_index: most_significant_index]
Example: boys [0:10]
- Most to least significant index
Array_name [most_significant_index: least_significant_index]
Example: boys [10:0]
As Verilog arrays are synthesizable they can be implemented in RTL code.
Types of Arrays in Verilog
Verilog arrays are further classified into different types depending upon their declaration and ability of modifications. The three major classifications of arrays are as follows:
- Packed or Fixed Arrays
Packed arrays or static array declarations include dimensions between type and data identifier. It can also be referred to as dimension declaration before object name. The packed arrays consist of a single type of data like bit, logic, and reg. The packed arrays do not allow arrays that have a predefined width. It is represented in contiguous bits during the simulation and synthesis of the design.
The minimum size of packed arrays is limited to 65536 (216) bits.
- Unpacked Arrays
Unpacked arrays are defined by declaring the dimensions after the object name. The data type that is associated with this array can vary and can include any data type. Every array defined in this section has an address associated with it. The address range is usually defined in the range of 1024 bits and they do not have to be contiguous in terms of memory.
- Multi-dimensional Arrays
Multidimensional arrays cannot be exactly termed as a type of array, rather it is an alternate way to declare an array in the code. The declaration can be done in both types packed and unpacked array types. It can be viewed as slices of a long array into multiple dimensions.
The grouping or declaration of an array in multidimensional can be used to logically group data and improve the readability using effective coding.
Operations on Arrays
Verilog Arrays are very simple and are used for simple operations, this makes the arrays to be accessible only through one element at a time. Users need to keep in mind that slicing of arrays is only applicable to one dimension. Apart from slicing, there are several other operations that you can effectively apply to Verilog arrays, the list of operations is as follows:
- Reading of array
Reading of arrays involves reading the entire array and copying it to another variable. The operation allows us to access the array and write it on a different variable.
Syntax:
A = B;
- Reading and writing
Reading and writing operation of the array allows us to iterate over the entire area and copy it to another array of the same size based on the index values.
Syntax:
A[i:j] = B[i:j];
- Reading and writing according to slice
The function is similar to reading and writing. The only difference here is we use the assignment operator to traverse over the elements of the array. It allows for making proper iterations and simultaneously writing the content on different variables.
Syntax:
A[x+:c] = B[y+:d];
- Reading a single element
If you do not want to iterate over the entire span of the array and look for a specific element you can address the same using a dedicated index value. In this operation, you can read the element from a particular index value and copy it to another variable.
Syntax:
A[i] = B[i];
- Equality
The equality operator helps us to check equality between two arrays. For instance, if you have two arrays you can iterate all the elements of the array according to the index and look for equality between the elements present in the array. It is the best way to compare the values of two arrays.
Syntax:
A[i:j] != B[i:j];
Limitations and alternative of Verilog Array
Verilog arrays are quite simple and plain, the only function these arrays perform is to group signals and create multidimensional structures. The arrays are used only for basic features and this makes the usage very limited. The initial syntax derived for Verilog arrays is also limited to 20 pages.
To overcome the limitations of Verilog Arrays we use SystemVerilog Arrays. SystemVerilog arrays are very flexible as compared to traditional Verilog arrays. It incorporates in itself a lot of features that include a wide range of operations and uses.
Operations on SystemVerilog Arrays.
SystemVerilog arrays can be used for both synthesizable RTL as well as nonsynthesizable test benches. These arrays can be effectively implemented to manipulate complex arrays and perform operations like slicing in multiple dimensions, locators, ordering, and reduction. We will see all these operations and what they signify.
- Locators
Array locators can be used to identify the index of a particular element in an array. This operation can be used on both packed and unpacked arrays. There are several inbuilt array locator methods some of the majorly used methods include element finder and index finder.
The syntaxes used in element finder are.
- find()
- find_first()
- find_last()
- min()
The syntaxes used in element finder are.
- find_index()
- find_first_index()
- find_last_index()
- unique()
- Ordering
The ordering operations are useful in reordering the elements of an area according to the application needed. The operator works on single-dimensional arrays and contains several built-in functions. Some of the built-in ordering functions are as mentioned below,
- reverse()
- sort()
- rsort()
- shuffle()
- Reduction
The reduction operator helps to convert all the elements of an array from a vector to scalar quantity. They perform bit operations and help to reduce the array size and structure according to requirements.
Conclusion
Verilog is considered to be one of the best hardware descriptive languages. The language is continuously developing and incorporates a lot of new functionalities which make the synthesis of the data easier and system-wide realizable.
Verilog Arrays are an integral part of Verilog HDL, it provides it with grouping functionality and allow the users to readily manipulate data in groups of similar data type. The system also overcomes the traditional limitations by implementing a new system called the SystemVerilog. The arrays are extremely useful and the operations associated with them allow the users to manipulate the data using different built-in functions.
