System Verilog- Synthesis and Verification

System Verilog

System Verilog has been claimed to be the first Hardware Description and Verification Language (HDVL) of the industry. This is because it merges the features of Hardware Description Languages like Verilog and VHDL with the features of specialized Hardware Verification Languages, such as C and C++.

In 2005, SystemVerilog became IEEE 1800TM (official IEEE standard) for the first time. Then in 2009, it was updated with IEEE 1800TM, and currently, it is in between the process of being modified further to work better using the guidance of Accellera as tool vendors.

As a result, users will gain experience over time by applying and practical implementation the language. As it is evolving ahead, SystemVerilog can find its practical implementation in the fields of productive and concise Assertion Based Verification, RTL Coding, and making coverage-driven verification surroundings by using constrained random techniques.

This hardware description and hardware verification language simulate, test, implement, and design electronic systems. SystemVerilog is influenced by Verilog and some of its extensions, and since 2008, it has been a part of the IEEE standard. However, it is most commonly used in semiconductor and electric design as an upgrade to Verilog.

A Brief History of System Verilog

The language took its initial steps by using Superlog language to Accellera in 2002 by the startup company named Co-Design Automation. SystemVerilog was then adopted as IEEE Standard 1800-2005, in the year of 2005. Finally, the standard was combined with the base Verilog, IEEE 1364-2005 standard, thus creating IEEE Standard 1800-2009. The latest version is IEEE standard 1800-2017.

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The set of features of SystemVerilog can be distinguished into two separate roles:

  • SystemVerilog is an extension of Verilog-2005 for the RTL (register-transfer level) design as all the features of the Verilog language are already available in SystemVerilog. Hence, Verilog can be considered to be the subset of SystemVerilog.
  • Now for verification, SystemVerilog uses extensive object-oriented programming techniques and that is more nearly associated with Java than Verilog. These constructs are usually not synthesizable.

Verilog vs SystemVerilog

Verilog was built with the intention mainly for gate- and register-transfer-level modeling and design. In 1995, it adapted the IEEE Standard 1364-1995 and was referred to as Verilog-95, then was revised in 2001 (referred to as Verilog-2001) and in 2005 again (then it was known as Verilog-2005). The revision done in 2005 included some of the minor spec clarifications and corrections. By the way, whenever the term ‘Verilog’ is being used, it is usually known as Verilog-2001.

Now, as technology and the digital system will move on to become more complex and grow bigger, the requirement for more sophisticated verification features will increase too. Unfortunately, the original Verilog language structure was not able to fulfill the demands of the progression. So in the year 2005, the extension of Verilog language was introduced, and it covered the verification functionalities, and later known as SystemVerilog, was added to the system. And over time, the extension became IEEE Standard 1800-2005.

After all the hurly-burly, finally, in 2009, SystemVerilog and Verilog were combined into one standard. The combined language was known to be SystemVerilog for unknown reasons. It came out to be IEEE 1800-2009 and after that, got revised again in 2012.

Now to sum it all up, these two standards have been modified as given below:

  • Before the year 2009: Till now, Verilog was for RTL modeling and design, and it was considered to be the main language. SystemVerilog was just the extension standard of Verilog and was meant for the verification.
  • After the year 2009: Verilog has ceased to exist anymore. SystemVerilog has become the main language and now it is used for RTL modeling and design, including verification.

System Verilog Simulators

HDL simulators simulate expressions that have been written in one of the hardware description languages, such as Verilog, SystemVerilog, VHDL.

Now, let’s have a look at the list of these software packages for making the SystemVerilog language work:

  • Incisive Enterprise Simulator (‘big 3’): Cadence, for starters, gained the Gateway Design, thus acquiring Verilog-XL language. To compete with the other fast simulators out there, Cadence made its compiled-language simulator, which is the NC-Verilog. The upgraded version of this NC-Verilog was called Incisive Enterprise Simulator, which has SystemVerilog support.

  • Active-HDL/Riviera-PRO: Now this is a simulator that provides a complete design environment targeted at FGPA applications. Aldec has given license to Active-HDL to Lattice Semiconductor, which is an FGPA vendor, and in Lattice’s design suites, the underlying engine could be found. AldecHDL is one of the cheapest products, but it also offers its user an expensive simulator that provides high performance, known as “Riviera-PRO”.

  • Speedsim: it is a cycle-based simulator that was initially programmed at DEC. The DEC developers have moved their way ahead by forming Quickturn Design Systems. Quickturn was later taken under by Cadence, who discarded the product in 2005. Speedsim also featured a creative slotted bit-sliced architecture that supported the simulation of almost 32 tests in number.

  • VCS (‘big 3’): This was developed originally by Peter Eichenberger, Michael McNamara, and John Sanguinetti when they started their own startup company, Chronologic Simulation, whose ownership was taken by ViewLogic Systems in 1994. VCS has modified continuously and mastered the compiled-code simulation, SystemVerilog support and native testbench, and unified compiler technologies.

  • ModelSim and Questa (‘big 3’): This was the first original simulator that was able to simulate Verilog and VHDL design entities together. Then in 2003, ModelSim version 5.8 became the first simulator to be able to run the features of the Accellera SystemVerilog 3.0 standard. Then in 2005, Mentor put forward Questa that provided SystemVerilog and Verilog simulation, and at the same time, expanded the Verification capabilities to advanced methodologies like Assertion Verification and Functional Coverage.

Synthesis and Verification Software

SystemVerilog has been extensively used in the design verification code in the chip-design industry. The three largest EDA vendors, Mentor Graphics, Synopsys, and Cadence Design Systems, all combined SystemVerilog in their mixed-language HDL simulators. However, there is not one simulator right now that can claim support for the shole SystemVerilog, making efforts to promote cross-vendor compatibility and testbench interoperability a challenge is underway.

In 2008, Mentor and Cadence launched the Open Verification Methodology, which is a useful framework and an open-source class library for facilitating the making of canned verification-IP and re-usable test benches. Whereas Synopsys, which was the first out of three to release a SystemVerilog class library (VMM), afterward gave a response back by introducing its proprietary VMM to the general public. And since then, there are many if third-party providers who have already released or announced the SystemVerilog verification IP.

The adaptation of SystemVerilog has been slow in the design synthesis role (transformation into a gate-netlist from a hardware-design description). Most of the design teams generally use design flows that involve numerous tools from various vendors. Several design teams cannot migrate to SystemVerilog RTL-design until the whole front-end tool suite (formal verification, linters, and automated test structure generators) supports a common language subset.

Scope and Purpose

Scope: The meaning of the language semantics and syntax for SystemVerilog, which provides a unified hardware design, verification language, and specification. This language usually includes design and modeling hardware at the register transfer level (RTL), behavioral, and gate-level abstraction levels. In addition, it is used for writing test benches by using assertions, coverage, constrained random verification, and object-oriented programming. The standard is also said to provide foreign programming languages to application programming interfaces (APIs).

Purpose: The standard has developed the IEEE 1800 SystemVerilog for meeting the increasing demands of usage of the language in design, verification, and specification of hardware. This revision of this standard edits and omits the errors of the language. Clearly, it clarifies the aspects of the language defined in IEEE Std 1800-2012.1 The revision focuses mainly on the upgraded features that make it easy to improve verification, ease design, and enhance cross-language interactions.


SystemVerilog Assertion acts as an observer as it observes the construct of the program. If it is built in that manner, it may also block the execution of the code, but it will not be able to alter the program. SystemVerilog has combined a set of different constructs that helps the users to make assertions and then precisely combine them with the rest of your verification code or design.

The major feature of SystemVerilog assertion is that they are one of the languages themselves. Now it means that you can use them with other language constructs in parallel, and there will be no need to create similar restrictions.

Frequently Asked Questions

  • What is a callback?

In computer programming, the callback is a code that is executed to pass as an argument for another code. This standard allows a software of lower-level layer to call out a function (or subroutine) in a higher-level layer.

  • What are the techniques to resolve the race condition occurring between RTL and Testbench when using SystemVerilog?

These are the given techniques to prevent the race condition occurring between RTL and Testbench when using SystemVerilog:

  • Clocking Block
  • Non-Blocking Assignments
  • Using Program Block
  • Distinguish between $urandom() and $random()?

For example, the $urandom system function drags a 32-bit unsigned random number every time it is commanded. While the $random system function drags, a 32-bit signed random number every time it is asked for.

System Verilog- Synthesis and Verification

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