Verilog Parameters- Module, and Overriding Parameters

Verilog Parameters

Parameters are constants in Verilog and do not correspond to any other data type, such as registers or nets. A constant expression is a number or a parameter that has been previously specified. We can’t change parameter values during runtime, but we can use the de param statement to change a parameter’s value. The def param statement can only change parameters during compilation. Let’s see Verilog Parameters in detail.

Parameters are Verilog components that make it possible to reuse a module with a different specification. A 4-bit adder, for example, may be parameterized to accept several bits as a value, and additional parameter values can be given in during module creation.

Module and Specify are the two sorts of parameters, and both allow a range specification. They are, however, manufactured as broad as the value to be stored. Thus a range specification is not required.

Module Parameters

It may be used to override parameter declarations in a module, causing the module to build with a new set of parameters. The de param statement can be used to change a parameter. For the parameter to be noticed quickly, it is usual to use capital characters in names. 

The parameters in the following module are used to indicate the bus width, data width, and FIFO depth in the design, and they may be changed with new values when the module is created or by using defparam statements.

module design_ip  ( addr, wdata, write, sel, rdata);  

     parameter  BUS_WIDTH    = 41,  

                DATA_WIDTH   = 69,  

                FIFO_DEPTH   = 513;  

     input addr;  

     input wdata;  

     input write;  

     input sel;  

     output rdata;  

     wire [BUS_WIDTH-1:0] addr;  

     wire [DATA_WIDTH-1:0] wdata;  

     reg  [DATA_WIDTH-1:0] rdata;  

     reg [7:0] fifo [FIFO_DEPTH];  


We can define parameters like: in the new ANSI format of Verilog port definition.

module design_ip  

    #(parameter BUS_WIDTH=41,  

        parameter DATA_WIDTH=69)   

           (input [BUS_WIDTH-1:0] addr,  

// other port declarations  


Overriding Parameters

During module instantiation, parameters can be overwritten with new values. The first portion is the d0 module, named design IP, and contains additional parameters ( ).

The second step is to utilize the defparam Verilog construct to set the new parameter values. In RTL designs, the first approach is often used to pass new parameters. In testbench simulations, the second technique is used to quickly alter design parameters without having to re-instantiate the module.

module tb;  

      // Module instantiation override  

     design_ip  #(BUS_WIDTH = 64, DATA_WIDTH = 128) d0 ( [port list]);  

    // Use of defparam to override  

    defparam d0.FIFO_DEPTH = 128;  


  • The module counter contains two parameters, N and DOWN, with default values of 2 and 0 respectively.
  • The amount of bits in the output is controlled by N, which essentially determines the counter’s breadth. By default, it’s a 2-bit counter.
  • The DOWN parameter determines whether the counter should increase or decrease. Because the parameter is set to 0, the counter will decrease.

2-bit up Counter

module counter  

  # ( parameter N = 2, parameter DOWN = 0)  

  (input clk, input rstn, input en, output reg [N-1:0] out);  

  always @ (posedge clk) begin  

    if (!rstn) begin  

      out <= 0;  

    end else begin  

      if (en)  

        if (DOWN)  

          out <= out – 1;  


            out <= out + 1;  


         out <= out;  




  • Even though it is not needed, the module counter is created with N equal to 2, which is the default number.
  • DOWN is not provided to the module when it is created. It has a default value of 0 and is hence an up-counter.

module design_top (input clk, input rstn, input en, output [1:0] out);  

    counter #(.N(2)) u0 (.clk(clk), .rstn(rstn), .en(en));  


  • The counter is implemented using the default settings, with N equaling two to make it a 2-bit counter and DOWN equaling zero to make it an up-counter. 
  • At the top level, the counter’s output is left disconnected.

4-bit down Counter

The module counter is created with N equal to 4, making it a 4-bit counter in this example. DOWN is given a value of 1 during module instantiation, resulting in the implementation of a down-counter.

module design_top (input clk, input rstn, input en, output [3:0] out);  

    counter #(.N(4), .DOWN(1))   

               u1 (.clk(clk), .rstn(rstn), .en(en));  


Specify Parameters 

The specparam keyword is used to specify these parameters, which give time and delay values. It can be used within the defined block as well as the main module body.

// Use of specify block  


    specparam  t_rise = 200, t_fall = 150;  

    specparam  clk_to_q = 70, d_to_q = 100;  


// Within main module  

module  my_block ( );  

    specparam  dhold = 2.0;  

    specparam  ddly  = 1.5;  

    parameter  WIDTH = 32;  


Difference Between Parameter And Localparam In Verilog

‘parameter’ is a module-specific term. Only within module boundaries may parameter declarations be made. It is referenced using the parameter name once it has been defined. It’s used to specify a module’s property. This property can be kept at its default value or changed when the module is created. As an example:

module adder(a,b,sum)

        parameter width = 8;

        input [width-1:0] a;

        input [width-1:0] b;

        output [width-1:0] sum;

        assign sum = a + b;


  • The adder is 8-bit by default (the width parameter uses the default assigned value of 8). The instantiator module, on the other hand, has the ability to modify parameter values.

module top;

    reg [15:0] a;

    reg [15:0] b;

    wire [15:0] sum1;

    wire [15:0] sum2;


    adder add1(a,b,sum1);

    defparam add1.width = 16;


    adder #(16) add2(a,b,sum2);


end module

Another way to define a parameter is to use the following syntax:

module adder #(parameter width = 8)


                      input [width-1:0] a,

                      input [width-1:0] b,

                      output [width-1:0] sum


         assign sum = a + b;


  • This feature allows you to change the parameters during the instantiation process, which is very useful when the DUT has numerous parameters.

module top;

    reg [15:0] a;

    reg [15:0] b;

    wire [15:0] sum1;

    wire [15:0] sum2;

   adder #(.SIZE(16)) add_0 (a,b,sum2);



Verilog 2001 additionally has a feature called “localparam,” which has the same scope as “parameter” but can’t be modified from the outside. Consider the following scenario:

module adder(a,b,sum)

        parameter height = 8;

        parameter width = 10;

        localparam length = 4;

        input [width-1:0] a;

        input [height-1:0] b;

        input [length-1:0] c;

        output [width-1:0] sum;

     assign sum = a + b + c;


module top

   reg [15:0] a;

   reg [15:0] b;

   wire [15:0] sum1;

   adder #(.width(16), .height(4), .length(5) add_0 (a,b,sum2); //error as length is not accessible outside the module adder


end module

In addition, the Verilog-2001 Standard does not extend the local param enhancement’s capabilities to the module header parameter list.

How To Override A Module Parameter?

During the instantiation of a module in Verilog, there are two ways for overriding a module parameter value.

  • The defparam keyword is used.
  • As well as parameter value assignment for module instance parameters.

The hierarchical path to the parameter and the parameter’s new value is given after the de param keyword. A constant expression should be used for this new value. Any parameters referenced by the right-hand side expression should be defined within the module where de param is called.

The technique for assigning the value of a module instance parameter appears to be similar to assigning a delay to a gate instance. This function overrides parameters in instantiated modules in the order in which they occur in the module. Parameters cannot be skipped in this format.

Constant expressions can contain parameters that have already been defined. Therefore, when changes to previously stated parameters are recognized, all parameters that rely on this value are automatically updated.

For example, a 4-bit adder may be parameterized to accept several bits value, and additional parameter values can be supplied during module creation. As a result, an N-bit adder becomes a 4-bit, 8-bit, or 16-bit adder. They’re similar to parameters provided to a function during a function call.

parameter MSB = 7;                  // MSB is a parameter with the constant value 7   

parameter REAL = 4.5;               // REAL holds the real number   

parameter FIFO_DEPTH = 256,  

          MAX_WIDTH = 32;           // Declares two parameters  

parameter [7:0] f_const = 2’b3;     // 2 bit value is converted into 8 bits; 8’b3 


A parameter is a variable that can be changed for each instantiation of a Verilog HDL module. These characteristics are used to specify variable width and the delay value, and they are commonly used to define constants. Defparam Statements or Module Instance Parameter Value Assignments are used to change parameters in Module Instantiations.


  • Why is parameter overriding needed in Verilog?
    This is a procedure in which the value of a parameter is set at the Scenario level and cannot be changed at the test case level. When one or more parameters may simply assume fixed values without the need for variability, you employ this feature.

  • What is Verilog?
    Verilog is a textual format for describing electrical circuits and systems that are based on the Hardware Description Language. Verilog is a programming language for an electrical design that may be used for verification through simulation, timing analysis, test analysis (testability analysis and fault grading), and logic synthesis.

  • What is the difference between overloading and overriding?
    Overloading occurs when two or more methods in the same class have the same name but distinct parameters. Overriding occurs when the method signature (name and arguments) in the superclass and the child class are identical.

  • Is Verilog hard?
    Verilog is not difficult to learn if you have any programming experience. It is simple to learn and has a syntactical resemblance to the C programming language.
Verilog Parameters- Module, and Overriding Parameters

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